Physical Design Engineer

2 weeks ago


Doha, Baladīyat ad Dawḩah, Qatar Robert Walters Full time

Job Requirements

  • Proficiency with Synopsys (ICC2 or FC & PrimeTime) / Cadence (Innovus & Tempus).
  • Execution of netlist-to-GDSII design flow, which includes tasks like floorplanning, power grid implementation, clock tree synthesis, place & route, and physical verification.
  • Experience in hierarchical design implementation, low-power design methodologies, achieving timing closure, conducting IR drop analysis, and crosstalk analysis.
  • Familiarity with TCL/Perl/Python scripting languages and design automation.
  • Essential experience in FinFET design, with additional experience in whole-chip integration being advantageous.


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